1. Field of the Invention
The present invention relates to a static memory (SRAM) that includes CMOS memory cells each having two cross-coupled inverters, each of which contains an n-channel transistor and p-channel transistor connected in series with each other. More particularly, this invention is concerned with a static memory having the area of each memory cell minimized.
2. Description of the Related Art
A important task concerning memories is to improve the degree of integration. For improving the degree of integration, conceivably, machining is carried out microscopically and novel circuitry is devised. It is also conceivable to devise a layout for minimizing the area of each memory cell. In a highly integrated memory, the degree of integration directly affects cost. Even if the area of each memory cell is decreased by only a few percent, a great effect can be expected.
The circuitry of a memory cell to be employed in a static memory (SRAM) is such that n-channel transistors are connected to a flip-flop (FF) and a pair of bit lines. Herein, the flip-flop is configured by cross-coupling two inverters in each of which an n-channel transistor and p-channel transistor are connected in series with each other. The n-channel transistors working as transfer gates are used for writing or reading.
A minimal spacing X between an n-channel transistor and p-channel transistor is restricted by a manufacturing process and the precision of manufacturing. The minimal spacing X must therefore be set to a correct value. In the past, contact holes, which join a polysilicon layer with a wiring layer and thus cross-couple a pair of inverters, have been centralized between n-channel transistors and p-channel transistors. This was thought to minimize the area of a memory cell.
In recent years, the technology of manufacturing semiconductors has progressed. A necessary minimal width of a device or a necessary minimal spacing between devices can be narrowed compared with a conventionally adopted one. According to a conventional layout, however, the size of a memory cell is not determined with a minimal spacing between an n-channel transistor and p-channel transistor. The size of a memory cell is determined with a spacing necessary to arrange contact holes among n-channel transistors and p-channel transistors. This poses a problem in that even when the technology of separating devices has advanced, the effect of diminishing a memory cell size is not realized.
Moreover, the size of a memory cell is affected by the distance by which a p-channel gate is extended across the channel in order to suppress a leakage current. When memory cells are set in an array, even if a variation in the manufacturing processes increases and the precision in manufacturing improves, the magnitude by which the p-channel gate is extended across the channel is not generally reduced. This leads to a problem in that the size of a memory cell cannot be decreased very much.